1. Field of the Invention
The present invention relates to a method for manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method for manufacturing a capacitor over bit line (COB) type of DRAM.
2. Description of the Related Art
DRAM is an important electronic component in the data communications industry. Advances in semiconductor processing techniques have yielded high-capacity DRAMs that occupy only a very small volume. Currently, the capacitor over bit line (COB) type of DRAM is widely adopted.
FIGS. 1A and 1B are schematic views showing the steps in producing a conventional COB type of DRAM.
As shown in FIG. 1A, a substrate 100 is provided. Shallow trench isolation (STI) structures 102 are formed in the substrate 100 so that an active region 104 is marked out. A word line structure 112 is formed by depositing a gate oxide layer 106, a gate electrode 108 and a cap layer 110 in sequence. Substrate regions having a lightly doped drain structures 114 are formed on each side of the word line structure 112. Spacers 116 are formed on the sidewalls of the word line structure 112. Source/drain terminals 118 are formed in the substrate 100. Dielectric material is deposited over the substrate 100 to form a first dielectric layer 120. A portion of the first dielectric layer 120 is removed to form a bit line contact opening 122 that exposes a source terminal 118.
As shown in FIG. 1B, a bit line structure 124 is formed over the first dielectric layer 120. The bit line structure 124 is electrically connected to the source terminal 118 via the bit line contact 122. Dielectric material is again deposited over the substrate 100 to form a second dielectric layer 126. A node contact opening 128 that passes through the second dielectric layer 126 and the first dielectric layer 120 and exposes the drain terminal 118 is formed. A node contact 130 is formed inside the node contact opening 128 so that the drain terminal is electrically linked. A capacitor structure 132 is formed above the second dielectric layer 126. The capacitor structure 132 is electrically connected to the drain terminal via the node contact 130. Since the node contact 130 and the bit line structure 124 are formed in different cross-sectional planes, dashed lines are used to outline the positions of the node contact opening 128 and the node contact 130 in FIG. 1B.
In the aforementioned method of forming COB type capacitor, the bit line contact opening in the first dielectric layer may be slightly misaligned. Therefore, a tighter design rule is often adopted for the bit line contact in order to prevent poor electrical connection or failure of the bit line contact to connect with the source terminal.
In addition, the first and the second dielectric layer have to be etched when the node electrode opening is formed. Because a thick layer of dielectric material needs to be removed, the etching process is harder. Furthermore, the aspect ratio of the node contact opening is relatively large. Hence, forming a node contact inside the node contact opening is a difficult process. Moreover, some voids are likely to form within the node contact, leading to a considerable increase in resistance between the node contact and the drain terminal.